DIL/NetPC ADNP/1520-3V: VHDL-based PIO

The default configuration of the ADNP/1520 high density PLD (CPLD) is a 20-bit parallel I/O port (PIO). This PIO offers the 8-bit port A (PA), the 8-bit port B (PB), and the 4-bit port C (PC). Each port is supported by two registers: one control register (PxCR) and one data register (PxDR). All registers are using I/O addresses within the x86 I/O address space between 0x30 and 0x37.

128-pin QIL Connector Pinout (PIO Signals)
Pin	Name	Group	Function
1	PA0	PIO	Parallel I/O (PIO), Port A, Bit 0 (ISP CPLD with VHDL-based PIO)
2	PA1	PIO	Parallel I/O (PIO), Port A, Bit 1 (ISP CPLD with VHDL-based PIO)
3	PA2	PIO	Parallel I/O (PIO), Port A, Bit 2 (ISP CPLD with VHDL-based PIO)
4	PA3	PIO	Parallel I/O (PIO), Port A, Bit 3 (ISP CPLD with VHDL-based PIO)
5	PA4	PIO	Parallel I/O (PIO), Port A, Bit 4 (ISP CPLD with VHDL-based PIO)
6	PA5	PIO	Parallel I/O (PIO), Port A, Bit 5 (ISP CPLD with VHDL-based PIO)
7	PA6	PIO	Parallel I/O (PIO), Port A, Bit 6 (ISP CPLD with VHDL-based PIO)
8	PA7	PIO	Parallel I/O (PIO), Port A, Bit 7 (ISP CPLD with VHDL-based PIO)
9	PB0	PIO	Parallel I/O (PIO), Port B, Bit 0 (ISP CPLD with VHDL-based PIO)
10	PB1	PIO	Parallel I/O (PIO), Port B, Bit 1 (ISP CPLD with VHDL-based PIO)
11	PB2	PIO	Parallel I/O (PIO), Port B, Bit 2 (ISP CPLD with VHDL-based PIO)
12	PB3	PIO	Parallel I/O (PIO), Port B, Bit 3 (ISP CPLD with VHDL-based PIO)
13	PB4	PIO	Parallel I/O (PIO), Port B, Bit 4 (ISP CPLD with VHDL-based PIO)
14	PB5	PIO	Parallel I/O (PIO), Port B, Bit 5 (ISP CPLD with VHDL-based PIO)
15	PB6	PIO	Parallel I/O (PIO), Port B, Bit 6 (ISP CPLD with VHDL-based PIO)
16	PB7	PIO	Parallel I/O (PIO), Port B, Bit 7 (ISP CPLD with VHDL-based PIO)
17	PC0	PIO	Parallel I/O (PIO), Port C, Bit 0 (ISP CPLD with VHDL-based PIO)
18	PC1	PIO	Parallel I/O (PIO), Port C, Bit 1 (ISP CPLD with VHDL-based PIO)
19	PC2	PIO	Parallel I/O (PIO), Port C, Bit 2 (ISP CPLD with VHDL-based PIO)
20	PC3	PIO	Parallel I/O (PIO), Port C, Bit 3 (ISP CPLD with VHDL-based PIO)

PIO I/O Address Usage
I/O Address	Register Name	Function	Direction
0x30	PACR	PIO Port A Control Register	R/W
0x31	PBCR	PIO Port B Control Register	R/W
0x32	PCCR	PIO Port C Control Register	R/W
0x33	---	Reserved	---
0x34	PADR	PIO Port A Data Register	R/W
0x35	PBDR	PIO Port B Data Register	R/W
0x36	PCDR	PIO Port C Data Register	R/W
0x37	---	Reserved	---

Register PACR (PIO Port A Control Register) Bit Usage
Bit	Name	Function
0	PACR0	PIO Bit PA0 Direction (0 = Input / 1 = Output)
1	PACR1	PIO Bit PA1 Direction (0 = Input / 1 = Output)
2	PACR2	PIO Bit PA2 Direction (0 = Input / 1 = Output)
3	PACR3	PIO Bit PA3 Direction (0 = Input / 1 = Output)
4	PACR4	PIO Bit PA4 Direction (0 = Input / 1 = Output)
5	PACR5	PIO Bit PA5 Direction (0 = Input / 1 = Output)
6	PACR6	PIO Bit PA6 Direction (0 = Input / 1 = Output)
7	PACR7	PIO Bit PA7 Direction (0 = Input / 1 = Output)

Register PBCR (PIO Port B Control Register) Bit Usage
Bit	Name	Function
0	PBCR0	PIO Bit PB0 Direction (0 = Input / 1 = Output)
1	PBCR1	PIO Bit PB1 Direction (0 = Input / 1 = Output)
2	PBCR2	PIO Bit PB2 Direction (0 = Input / 1 = Output)
3	PBCR3	PIO Bit PB3 Direction (0 = Input / 1 = Output)
4	PBCR4	PIO Bit PB4 Direction (0 = Input / 1 = Output)
5	PBCR5	PIO Bit PB5 Direction (0 = Input / 1 = Output)
6	PBCR6	PIO Bit PB6 Direction (0 = Input / 1 = Output)
7	PBCR7	PIO Bit PB7 Direction (0 = Input / 1 = Output)

Register PCCR (PIO Port C Control Register) Bit Usage
Bit	Name	Function
0	PCCR0	PIO Bit PC0 Direction (0 = Input / 1 = Output)
1	PCCR1	PIO Bit PC1 Direction (0 = Input / 1 = Output)
2	PCCR2	PIO Bit PC2 Direction (0 = Input / 1 = Output)
3	PCCR3	PIO Bit PC3 Direction (0 = Input / 1 = Output)
4	---	Reserved
5	---	Reserved
6	---	Reserved
7	---	Reserved

Register PADR (PIO Port A Data Register) Bit Usage
Bit	Name	Function
0	PADR0	PIO Bit PA0 Read or Write (Read if Bit = Input / Write if Bit = Output)
1	PADR1	PIO Bit PA1 Read or Write (Read if Bit = Input / Write if Bit = Output)
2	PADR2	PIO Bit PA2 Read or Write (Read if Bit = Input / Write if Bit = Output)
3	PADR3	PIO Bit PA3 Read or Write (Read if Bit = Input / Write if Bit = Output)
4	PADR4	PIO Bit PA4 Read or Write (Read if Bit = Input / Write if Bit = Output)
5	PADR5	PIO Bit PA5 Read or Write (Read if Bit = Input / Write if Bit = Output)
6	PADR6	PIO Bit PA6 Read or Write (Read if Bit = Input / Write if Bit = Output)
7	PADR7	PIO Bit PA7 Read or Write (Read if Bit = Input / Write if Bit = Output)

Register PBDR (PIO Port B Data Register) Bit Usage
Bit	Name	Function
0	PBDR0	PIO Bit PB0 Read or Write (Read if Bit = Input / Write if Bit = Output)
1	PBDR1	PIO Bit PB1 Read or Write (Read if Bit = Input / Write if Bit = Output)
2	PBDR2	PIO Bit PB2 Read or Write (Read if Bit = Input / Write if Bit = Output)
3	PBDR3	PIO Bit PB3 Read or Write (Read if Bit = Input / Write if Bit = Output)
4	PBDR4	PIO Bit PB4 Read or Write (Read if Bit = Input / Write if Bit = Output)
5	PBDR5	PIO Bit PB5 Read or Write (Read if Bit = Input / Write if Bit = Output)
6	PBDR6	PIO Bit PB6 Read or Write (Read if Bit = Input / Write if Bit = Output)
7	PBDR7	PIO Bit PB7 Read or Write (Read if Bit = Input / Write if Bit = Output)

Register PCDR (PIO Port C Data Register) Bit Usage
Bit	Name	Function
0	PCDR0	PIO Bit PC0 Read or Write (Read if Bit = Input / Write if Bit = Output)
1	PCDR1	PIO Bit PC1 Read or Write (Read if Bit = Input / Write if Bit = Output)
2	PCDR2	PIO Bit PC2 Read or Write (Read if Bit = Input / Write if Bit = Output)
3	PCDR3	PIO Bit PC3 Read or Write (Read if Bit = Input / Write if Bit = Output)
4	---	Reserved
5	---	Reserved
6	---	Reserved
7	---	Reserved