DIL/NetPC DNP/1486
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DIL/NetPC DNP/1486-3V: Using the PIO
The DIL/NetPC DNP/1486-3V 20-bit general purpose parallel I/O (PIO) signals are based on 20 I/O pins of the AMD Elan SC410 32-bit microcontroller. The following table shows the details. For more information about the AMD Elan SC410 32-bit microcontroller please use the AMD SC400/SC410 literature.
DNP/1486-3V PIO Signals
Pin
Name
Function
AMD SC410 Signal Name
1
PA0
Parallel I/O, Port A, Bit 0
GPIO24
2
PA1
Parallel I/O, Port A, Bit 1
GPIO25
3
PA2
Parallel I/O, Port A, Bit 2
GPIO26
4
PA3
Parallel I/O, Port A, Bit 3
GPIO27
5
PA4
Parallel I/O, Port A, Bit 4
GPIO28
6
PA5
Parallel I/O, Port A, Bit 5
GPIO29
7
PA6
Parallel I/O, Port A, Bit 6
GPIO30
8
PA7
Parallel I/O, Port A, Bit 7
GPIO31
9
PB0
Parallel I/O, Port B, Bit 0
GPIO16
10
PB1
Parallel I/O, Port B, Bit 1
GPIO17
11
PB2
Parallel I/O, Port B, Bit 2
GPIO18
12
PB3
Parallel I/O, Port B, Bit 3
GPIO19
13
PB4
Parallel I/O, Port B, Bit 4
GPIO20
14
PB5
Parallel I/O, Port B, Bit 5
GPIO21
15
PB6
Parallel I/O, Port B, Bit 6
GPIO22
16
PB7
Parallel I/O, Port B, Bit 7
GPIO23
17
PC0
Parallel I/O, Port C, Bit 0
GPIO12
18
PC1
Parallel I/O, Port C, Bit 1
GPIO13
19
PC2
Parallel I/O, Port C, Bit 2
GPIO14
20
PC3
Parallel I/O, Port C, Bit 3
GPIO15
DIL/NetPC DNP/1486-3V: PIO Control Registers
The access to the DIL/NetPC DNP/1486-3V 20-bit general purpose parallel I/O signals is going over six AMD Elan SC410 special functions registers. There are two registers for each port, one mode register (PxMR) and one data register (PxDR). With the mode register, the input or output mode is set for each PIO bit. Over the data register, you can read the current of a input bit or write to a output bit.
The six mode and data registers are index registers within the AMD Elan SC410 chip setup and control (CSC) register space. These registers are indirectly accessible to the programmer by using a Chip Setup and Control Index Register (CSCIR) and a Chip Setup and Control Data Register (CSCDR).
DNP/1486-3V PIO Control Registers
Name
Function
SC410 Register
Addressing
CSCIR
Chip Setup and Control Index Register
Index Register for Index Pointer
I/O Adr. 22h
CSCDR
Chip Setup and Control Data Register
Data Register for Data R/W
I/O Adr. 23h
PAMR
Port A Mode Register
GPIO Function Select Register F
I/O Adr. 22h/23h Index A5h
PADR
Port A Data Register
GPIO Read-Back/Write Register D
I/O Adr. 22h/23h Index A9h
PBMR
Port B Mode Register
GPIO Function Select Register E
I/O Adr. 22h/23h Index A4h
PBDR
Port B Data Register
GPIO Read-Back/Write Register C
I/O Adr. 22h/23h Index A8h
PCMR
Port C Mode Register
GPIO Function Select Register D
I/O Adr. 22h/23h Index A3h
PCDR
Port C Data Register
GPIO Read-Back/Write Register B
I/O Adr. 22h/23h Index A7h
All registers within the AMD Elan SC410 chip setup and control (CSC) register space are accessed through a mechanism called "indexed". This mechanism uses direct- mapped I/O index and data registers to expand the I/O space for reading and writing internal system registers. The access to the mode and data registers are illustrated in the following picture.
The picture shows the example of writing the value FFh to the CSC index A9h. All the AMD Elan SC410 chip setup and control (CSC) registers are accessed using a two-step process:
Within a program make sure that no interrupt occurs after the first I/O write. If the interrupt handler changes the content of the Chip Setup and Control Index Register (CSCIR) at I/O address 22h, the second I/O access after return from the interrupt uses not the correct register. Disable all interrupts before the first I/O write and enable the interrupts after the second I/O read or write. Use allways the following code fragment:
disable (); // Disable Interrupts
outportb (0x22, ....); // Set IndexPointer to ....
outportb (0x23, ....); // Read or Write Data from/to .... here
enable (); // Enable Interrupts
DIL/NetPC DNP/1486-3V: DOS Sample Code
The following C source code is a simple example for using the DNP/1486-3V 20-bit general purpose parallel I/O (PIO) signals on the DIL/NetPC evaluation board DNP/EVA1. On this evaluation board, the PIO Port A of the DNP/1486-3V is connected to 8 LEDīs and PIO Port B to a 8-position DIP switch.
It is necessary within this sample to set the bits for Port A as output and for Port B as input. After this setup, to turn a LED on, write a 1 to a Port A bit. If a DIP switch position on, you read a 1. The sample program first perform the setup operation. Then, the program reads in a loop the current state of the DIP switch on Port B and shows this state over the LEDīs on Port A.
// DIP-Switch Read Demo for DIL/NetPC DNP/1486-3V (DOS-Version)
// Written by KDW - 12.Mar.2000
#include ‹stdio.h›
#include ‹stdlib.h›
#include ‹conio.h›
#include ‹dos.h›
#define CSCIR 0x22 // Chip Setup and Control Index Register
#define CSCDR 0x23 // Chip Setup and Control Data Register
#define PAMR 0xa5 // PIO Port A Mode Register
#define PADR 0xa9 // PIO Port A Data Register
#define PBMR 0xa4 // PIO Port B Mode Register
#define PBDR 0xa8 // PIO Port B Data Register
void main (void) {
int iDIPsw, iDIPswMirror;
// Set SC410 for DIL/NetPC PIO Port A = Output
disable ();
outportb (CSCIR, PAMR); // Set IndexPointer to IndexRegister A5h
outportb (CSCDR, 0xff); // IndexRegister A5h= 0xff (Output)
// Set SC410 for DIL/NetPC PIO Port B = Input
outportb (CSCIR, PBMR); // Set IndexPointer to IndexRegister A4h
outportb (CSCDR, 0x00); // IndexRegister A4h= 0x00 (Input)
// Build DIP-Switch Status Mirror
outportb (CSCIR, PBDR); // Set IndexPointer to IndexRegister A8h
iDIPswMirror= inportb (CSCDR); // Read IndexRegister A8h
enable ();
// Show current DIP-Switch Status (Message and LEDīs)...
printf ("\n DIP-Switch= 0x%02x", iDIPswMirror & 0xff);
disable ();
outportb (CSCIR, PADR);
outportb (CSCDR, iDIPswMirror & 0xff);
enable ();
// Read DIP-Switch and show Status until User Break...
while (kbhit () == 0) {
// Read current DIP-Switch Status.
disable ();
outportb (CSCIR, PBDR); // Set IndexPointer to IndexRegister A8h
iDIPsw= inportb (CSCDR); // Read IndexRegister A8h
enable ();
// Compare current Status with last Status
if (iDIPsw != iDIPswMirror) {
// DIP-Switch Status change...
iDIPswMirror= iDIPsw;
printf ("\b\b%02x", iDIPsw & 0xff); // Update Message
disable ();
outportb (CSCIR, PADR); // Update LEDīs
outportb (CSCDR, iDIPsw & 0xff);
enable ();
}
}
printf ("\n");
}
The source code was written for Borland Turbo C / C++. For using this code with other compilers and operating systems, please note that we use some special Borland runtime functions.The following table contains a list of this special C functions.
Special Borland Runtime Functions
Name
Function
disable ()
Disable the Processor Interrupts
enable ()
Enable the Processor Interrupts
inportb ()
Read a Byte from a I/O Input Port (Byte I/O Input)
outportb ()
Write a Byte to a I/O Output Port (Byte I/O Output)
DIL/NetPC DNP/1486-3V: Linux Sample Code
The following C source code is a simple example for using the DNP/1486-3V 20-bit general purpose parallel I/O (PIO) signals on the DIL/NetPC evaluation board DNP/EVA1 with a Linux program. This program is using direct x86 I/O access form the Linux user space. The program implements a simple 8-bit counter. The output of this counter drives the evaluation board LEDs.
// Counter Demo for DIL/NetPC DNP/1486-3V
// Written by KDW - 12.Mar.2000
// Update for Linux by MHA - 19.Jul.2000
#include ‹stdio.h›
#include ‹fcntl.h›
#include ‹unistd.h›
#include ‹asm/io.h›
#define CSCIR 0x22 // Chip Setup and Control Index Register
#define CSCDR 0x23 // Chip Setup and Control Data Register
#define PAMR 0xa5 // PIO Port A Mode Register
#define PADR 0xa9 // PIO Port A Data Register
int ioperm (int, int, int); // Allows direct x86 I/O access from User Space
int main (void) {
int iCnt;
printf (" Start Binary Counter for Port A...\n");
printf (" Current Counter Value= 0");
// Set SC410 for DIL/NetPC PIO Port A = Output
ioperm (CSCIR, 2, 1);
outb (PAMR, CSCIR); // Set IndexPointer to IndexRegister A5h
outb (0xff, CSCDR); // IndexRegister A5h= 0xff
ioperm (CSCIR, 2, 0);
// Run Counter until User Break by CTRL-C...
for (;;) {
// Write 8-bit Binary Counter Value to Port A...
for (iCnt= 0; (iCnt < 256); iCnt++) {
ioperm (CSCIR, 2, 1); // Enable CSCIR/CSCDR access
outb (PADR, CSCIR); // Set IndexPointer to IndexRegister A9h
outb (iCnt & 0xff, CSCDR); // IndexRegister A9h= iCnt
ioperm (CSCIR, 2, 0); // Disable CSCIR/CSCDR access
printf ("\r Current Counter Value= %3d", iCnt);
fflush (stdout);
usleep (100000); // Delay
}
}
return (0);
}
The C sample source works with any x86 GNU C compiler. Please use the compiler parameter -O within your GNU tool chain. Please note that we use some special GLIBC runtime functions. The following table contains a list of this special x86 GLIBC functions.
Special GLIBC Runtime Functions
Name
Function
ioperm ()
Enable or Disable the access for a x86 I/O address range
outb ()
Write a Byte to a x86 I/O Output Port (Byte I/O Output)
inb ()
Read a Byte from a x86 I/O Output Port (Byte I/O Input)
usleep ()
Wait/Sleep (for) some microseconds (Delay)
DIL/NetPC DNP/1486-3V: PIO 5 Volt Tolerance
It is to be considered, however, that the DIL/NetPC DNP/1486-3V is a 3.3 volt- based system. The output levels of the parallel I/O signals are derived from the 3.3 volt supply voltage. If these signals are inputs, not all inputs can be driven by external 5 volt components. The following table shows more details.
DNP/1486-3V PIO Signals
Pin
Name
Function
5V Tolerant if Input
1
PA0
Parallel I/O, Port A, Bit 0
YES
2
PA1
Parallel I/O, Port A, Bit 1
YES
3
PA2
Parallel I/O, Port A, Bit 2
YES
4
PA3
Parallel I/O, Port A, Bit 3
YES
5
PA4
Parallel I/O, Port A, Bit 4
YES
6
PA5
Parallel I/O, Port A, Bit 5
YES
7
PA6
Parallel I/O, Port A, Bit 6
YES
8
PA7
Parallel I/O, Port A, Bit 7
YES
9
PB0
Parallel I/O, Port B, Bit 0
No
10
PB1
Parallel I/O, Port B, Bit 1
No
11
PB2
Parallel I/O, Port B, Bit 2
No
12
PB3
Parallel I/O, Port B, Bit 3
No
13
PB4
Parallel I/O, Port B, Bit 4
No
14
PB5
Parallel I/O, Port B, Bit 5
No
15
PB6
Parallel I/O, Port B, Bit 6
No
16
PB7
Parallel I/O, Port B, Bit 7
No
17
PC0
Parallel I/O, Port C, Bit 0
No
18
PC1
Parallel I/O, Port C, Bit 1
No
19
PC2
Parallel I/O, Port C, Bit 2
No
20
PC3
Parallel I/O, Port C, Bit 3
No
SSV EMBEDDED SYSTEMS. Board Level Products. File: dnp0005.htm, Last Update: 07.Jan.2012
Copyight (c) 1996 - 2012 SSV and KDW. All rights reserved. webmaster@ist1.de